A dual in-line memory module “DIMM” may include a number of individual dynamic random access memory “DRAM” chips on a printed circuit board. Each DRAM chip may include a command/address/control bus and may be connected to the motherboard using a separate databus “DQ” having a number of data lines. The double data rate “DDR” command/address/control bus may be routed in parallel with a clock that may be ½ the rate of the data bus. The control timing may be valid on every rising edge of clock (i.e., 1N timing) while the address and command bus may be valid on any rising edge that is qualified by the control signal (e.g., CS# signal). Hence, the address/command bus may be valid for every rising edge of clock (1N), every other rising edge of clock (2N), etc. The address/command bus typically includes more loads as it may cover all the ranks on a DIMM, as well as multiple DIMMs per channel (e.g., a two DIMM per channel system loaded 2R in each slot would have 4× the address/command loading of control, which only has 1 rank loading). The number of ranks on any DIMM may refer to the number of independent sets of DRAMs that may be accessed simultaneously for the full data bit-width of the DIMM to be driven on the bus. Control signals such as chip select “CS#” and on-die termination “ODT” control may be rank specific and may run at faster 1N timings.
As the DQ bus speed increases, the clock and associated command/address/control bus frequencies may also increase. Since there may be a difference in bus architectures and/or loading, the command/address/control bus may be bandwidth limited before the data bus or clocks. For instance, if DDR4 extends the data bus to 3.2 Gigabits per second (Gbps, or simply GT) (EOL frequency target), the maximum clock rate may be 1.6 GHz and the control rate may be 1.6GT (or 800 MHz). The control bus may limit at approximately 1.2GT, which may essentially limit the maximum bandwidth of the entire interface.
According to the Joint Electron Device Engineering Council “JEDEC”, one proposed method of solving this problem is to essentially run at a ¼ rate external/internal receive clock frequency. However, the address/command/control buses run at DDR3 rates. This may leave performance on the table as a command cannot be issued per ½ rate clock. This may create a significant problem for the DDR3/DDR4 crossover where DDR4 performance would be hampered by this constraint. One possible method may involve doubling the number of pins, however, the control bus may have a difficult time running at these higher frequencies even with reduced loads.